1. Field of the Invention
The present invention relates in general to a semiconductor integrated circuit, and more particularly to a technique of selecting a signal used therein.
2. Description of the Background Art
FIG. 18 is a circuit diagram showing a configuration of conventional signal selecting means 200 in a conventional semiconductor integrated circuit. The signal selecting means 200 comprises a mode determination unit 6 and a logical processing unit 7.
In the logical processing unit 7, signal conductors 21 to 24 are connected to input ends of AND gates 3a to 3d respectively, and input signals P.sub.1 to P.sub.4 fed to the signal conductors 21 to 24 can be transmitted to an input end of an OR gate 4 only when the AND gates 3a to 3d are open, respectively. The AND gates 3a to 3d are open in mutually exclusive manner, so that only one of the input signals P.sub.1 to P.sub.4 can become an effective input for the OR gate 4 and an output end of the OR gate 4 outputs the one of input signals P.sub.1 to P.sub.4 as effective data OUT.
The mode determination unit 6 is provided for the purpose of opening the AND gates 3a to 3d in mutually exclusive manner as mentioned above. In the mode determination unit 6, a decoder 5 outputs four control signals S.sub.00 to S.sub.03 to the respective other input ends of the AND gates 3a to 3d. The four control signals S.sub.00 to S.sub.03 are generated by decoding a 2-bit mode signal M.sub.1 M.sub.2 fed to the decoder 5.
FIG. 19 is a conversion table of decoding. According to the four possible combinations of logical values of the 2-bit mode signal M.sub.1 M.sub.2, the control signals S.sub.00 to S.sub.03 to be outputted from the decoder 5 take the logical value "1" in mutually exclusive manner. For example, when the mode signal M.sub.1 M.sub.2 takes the logical values "1", "0", P.sub.2 is taken as the data OUT. In order to perform such decoding operation, the decoder 5 is supplied with a decoding clock CKD from the outside.
Thus, the signal selecting means 200 has a function of selectively outputting only one of the input signals P.sub.1 to P.sub.4 applied from the outside in accordance with the 2-bit mode signal M.sub.1 M.sub.2 also applied from the outside.
As described with respect to the signal selecting means 200, in the prior art, a mode signal having a plurality of bits are required for selectively outputting a plurality of input signals applied from the outside. As the integrated circuit processes a greater deal of logical values, the number of the input signals to be selected becomes larger. In the prior art technique, this also invites an increase of the number of bits of the mode signal and accordingly, the number of input terminals for receiving them. Therefore, there arises the great disadvantage of inviting degradation of integration which is an important factor in the integrated circuit.
Conversely, there is the problem that if the number of input terminals for receiving the mode signal is fixed, the number of input signals to be selected should be limited.
Furthermore, in decoding, the decoding clock should be supplied from the outside and a terminal for receiving it is further required.